1. Field of the Invention
This invention relates to a method of fabricating integrated circuit devices having electrically isolated mesas and the structure.
2. Brief Description of the Prior Art
In the fabrication of integrated circuits, it is often necessary to provide one or more levels of interconnect on the chip. Since the levels of interconnect are generally current carrying metals and the levels of interconnect are separated from each other and from the substrate by an insulator, there effectively exists a capacitor between the interconnect levels themselves and between interconnect levels and the substrate, resulting in a capacitive effect between the layers of interconnect per se and/or the substrate. It is well known that this capacitive effect reduces the operating speed of the integrated circuit. Accordingly, the art is constantly attempting to find ways to decrease the capacitive effect between layers of interconnect and/or the substrate in order to increase the speed of circuit operation.
The above described problem also exists in integrated circuits having plural spaced apart mesas wherein the interconnects travel between the mesas over buried oxide layers disposed between the mesas as well as with interconnects travelling between elements in a single mesa. In such arrangements, there is a capacitance set up between the interconnect, which can be metal or doped semiconductor material, generally doped silicon, and the substrate as well as between adjacent mesas.